This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
FIGS. 1A-1B show block diagrams of conventional circuitry without physical interleaving 100A and with physical interleaving 100B with size 2, such as, e.g., having 2 multiplexers (i.e., MUX2). As shown, neighboring bits from a same word (e.g., w0b0 and w0b1) are placed twice (2×) the distance away as compared to non-interleaved bits. In this instance, the interleaved bits may be more resistant to errors. Generally, interleaving is used in digital communication and storage systems to improve the performance of error correcting codes (ECC), which have bounded detection and correction capabilities (e.g., of up to X number of data bits) for each data word. For instance, SECDED (Single-Error-Correction-Double-Error-Detection) ECC may correct a 1-bit error and detect a 2-bit error. Sometimes, if a multi-cell upset (MCU) causes a 2-bit error in a data word, SECDED ECC may detect the error, but SECDED ECC may not be able to correct the error.
As such, physical interleaving (i.e., multiplexing multiple bit lines) may be used for memory with ECC to handle MCU. Physical interleaving may be achieved by grouping the same bit from multiple words to share the same MUX, so that neighboring bits from the same word are physically distant. For instance, as shown in FIGS. 1A-1B, physical interleaving may use a 2-input MUX (MUX2), and in this instance, w0b0 and w0b1 are thus placed further away (i.e., more physically distant) from each other, thereby reducing the probability that both bits are affected by MCU. Along with MUX2, the circuitry may also include sense amplifier circuitry (SA) to perform known functions.
Further, in some instances, both the probability and the number of bits in MCU may increase with use of lower supply voltage. As such, use of lower supply voltage may call for even larger physical interleaving sizes, especially in support of runtime low-voltage operations, such as, e.g., data retention mode. Unfortunately, in some instances, a large amount of physical interleaving may cause an imbalance in footprint aspect ratio, which may affect memory power, performance, and area (PPA). Generally, in various scenarios, different physical interleaving options (e.g., different MUX options) may result in different memory aspect ratios and may have significant impact on area, read/write power, and some effects on delay and standby power.